ASML (ASML) and Chip Giants like TSMC Plot a Bigger Canvas for Building AI Chips

A leading lithography developer is pursuing a bold expansion of its extreme ultraviolet printing capability by adopting larger mask formats to fabricate bigger data-center chips. The plan centers on partnerships with major customers to adapt the high‑NA EUV workflow so it can print devices that surpass the size limits of today’s standard masks. The aim is to unlock new levels of productivity and enable the production of larger AI-focused processors.

The core concept involves moving beyond the current size ceiling by introducing larger mask formats. The roadmap calls for a pilot production line to start around 2031, followed by high‑volume manufacturing readiness by 2033. Early analyses suggest these changes could lift system productivity by about 40%, creating potential upside for the tooling ecosystem and for customers aiming to scale up their AI accelerators.

Bull Case: Why the move could reshape growth

If successful, the larger‑mask approach would open a fresh growth corridor for the lithography leader and help partners manufacture significantly bigger AI chips more efficiently. The technology would extend the High NA EUV platform beyond current chip-size constraints, potentially driving stronger demand for next‑generation tooling. Early engagement with a major customer provides a credible path to market, signaling readiness to adopt larger-chip production in the coming years. This collaboration could also deepen ties with one of the industry’s largest buyers, offering the supplier clearer visibility into future equipment needs.

Beyond chip size, the initiative would help the customer prepare manufacturing processes for the next era of AI hardware, where larger, more capable processors are becoming the standard. For the tooling maker, the project broadens the scope of the High NA roadmap, while enabling the customer to sustain a competitive edge in advanced-node manufacturing. In essence, it represents a strategic bet on a scalable platform capable of printing progressively bigger and more complex devices.

Bear Case: Timelines and near‑term impact

Even with optimistic projections, the program is unlikely to contribute meaningful revenue in the near term. The milestones are spaced years apart—2031 for a pilot line and 2033 for full‑scale production—so investors should not expect a quick lift in results. Realized benefits hinge on successful integration with customer manufacturing flows, cost-efficient production of larger masks, and broad market adoption among AI‑heavy workloads.

Risks include potential delays in tooling performance, unforeseen process challenges, or shifts in demand for unusually large AI chips. The competitive landscape and evolving fabrication approaches could also influence how quickly the technology gains widespread use. Nevertheless, the effort signals a long‑term strategic push to expand lithography capabilities in step with the demand for more powerful AI hardware.

In summary, the initiative marks a deliberate attempt to broaden the reach of High NA EUV tooling, with the potential to unlock a new class of large‑chip production. If the timelines hold, it could incrementally improve efficiency for top manufacturers and shape how the next generation of AI processors is built, while helping the provider secure a deeper role in the trajectory of advanced semiconductor manufacturing.